Along with an increase in the functionality of an LSI (i.e., large scale integrated circuit), there has been an increasing number of mixed-signal LSIs that are provided with both an analog circuit and a digital circuit. In a digital circuit, a number of circuit parts operate in synchronization with a clock signal. Because of this, a large-scale circuit consumes a large electric current at the transition of a clock signal, thereby creating an IR drop in the power supply voltage and the ground voltage. Such an IR drop includes high frequency components that are in synchronization with the clock frequency, and, thus, a power-supply bypass condenser or the like provided in the LSI may not produce a sufficient suppressive effect. An IR drop adversely affects the characteristics of an analog circuit and the timing margin of a digital circuit.
A technology for compensating for an IR drop includes a method of introducing different skews in clock signal lines that are laid out in a digital circuit. With this arrangement, these skews serve to distribute peaks of electric-current consumption that are in synchronization with the clock signal, thereby improving the worst value of an IR drop. However, the fact that the IR drop causes a drop in the power-supply voltage remains to be true, and drastic improvements cannot be obtained in the analog characteristics or in the timing margins.
There is another method for improving an IR drop, which utilizes enable signals provided for controlling whether logic circuits in the digital circuit operate or do not operate, so that the amount of electric current supplied from the power-supply circuit is adjusted according to the enable signals. This method serves to stabilize the power-supply-voltage fluctuation that is created at the start or end of an operation of a logic circuit, but cannot cope with an IR drop that contains high frequency components synchronized with a clock signal frequency.    [Patent Document 1] Japanese Laid-open Patent Publication No. 6-84357    [Patent Document 2] Japanese Laid-open Patent Publication No. 11-219586